Modern microprocessors operate on wide-bit words. For example, it is conventional for some microprocessors to process 64-bit words. As processor clock rates increase ever higher, the routing of such relatively wide-bit words on wide-bit buses becomes problematic. At high transmission speeds, the inevitable skew with regard to propagation on separate traces in the wide-bit buses may lead to unacceptable bit error rates. Moreover, such buses demand a lot of power and are expensive to design.
To enable the high-speed transmission of data words without the skew and distortion issues associated with high-speed wide-bit buses, serializer-deserializer (SERDES) systems have been developed. A SERDES transmitter serializes the data words into a high-speed serial data stream. A SERDES receiver receives the high-speed serial data stream and deserializes it back into the parallel data words. The serial transmission is usually differential and includes an embedded clock. The skew and distortion issues associated with high-speed wide-bit data buses are thus abated.
Although SERDES systems enable very high-speed data transmission such as 10 gigabits per second or even higher rates, the transmission characteristics for the differential serial data channel between the transmitter and receiver are not linear across the corresponding Nyquist bandwidth of 5 Ghz. Instead, the channel has a frequency-dependent response that reduces the amplitude of the higher-frequency portions of the data bandwidth. To counter the resulting distortion, the SERDES receiver includes an amplifier that is not linear across the frequency spectrum but instead emphasizes the higher frequency bands for the received data spectrum.
To provide this frequency-dependent amplification as shown in FIG. 1, a conventional SERDES receiver amplifier may include a first-stage transconductance amplifier stage 105 that drives a second-stage transimpedance amplifier stage 110. Within first stage 105, a differential pair of transistors M1 and M2 are biased by current sources I1 and I2. These current sources in combination create a bias current that is steered between transistors M1 and M2 responsive to a differential input voltage formed from input voltages IN and INX that drive the gates of transistors M1 and M2, respectively. The resulting difference in the currents conducted by transistors M1 and M2 produces a voltage difference at their drains, which are coupled to a power supply through load resistors RL. Transimpedance amplifier 115 in second stage 110 amplifies the differential voltage across the drains of transistors into a differential output voltage formed from output voltages OUT and OUTX. The second-stage 110 includes a negative feedback loop formed by a differential pair of transistors M3 and M4 that are biased by a current source I3. For example, suppose that a drain voltage VM3 for transistor M3 is higher than a drain voltage VM4 for transistor M4. Transimpedance amplifier 115 will then swing output voltage OUTX higher than output voltage OUT. If this change in the drain voltages is relatively low frequency, the high value for output voltage OUTX will pass through a low pass filter (LPF) to turn transistor M3 on. Transistor M3 will then discharge its drain voltage VM3, which reduces the difference between drain voltages VM3 and VM4. In contrast, if the change in the drain voltages was relatively high frequency, drain voltage VM3 would remain higher than drain voltage VM4. The negative feedback through the low pass filters and the differential pair of transistors M3 and M4 thus reduces the gain for second stage amplifier 110 at the lower frequencies. But this reduction of gain required the discharging of the drain voltages VM3 and VM4 and thus increases power consumption. Moreover, the use of two stages for amplification demands a lot of die area.
Accordingly, there is a need in the art for improved amplifiers providing high-frequency emphasis over a wideband width while having greater density and reduced power demands.